1. Field
The present invention relates to a method of communication suitable for use in a digital electronics system. The method is particularly but not exclusively suitable for communication between components within a computer chip, or between discrete components on a circuit board.
2. Background
Delay insensitive communication is an attractive communication method in which data can be correctly received even if delays occur during its communication. Delay insensitive communication is particularly applicable in asynchronous systems. Although many possible delay insensitive coding techniques exist, very few of these can be efficiently implemented in complementary metal-oxide semiconductor (CMOS) logic design.
A popular form of delay insensitive coding is the so called “m-of-n” code, where communication is carried out using an n bit binary word, and all valid communication values have m bits set to a predetermined value. Using an m-of-n code, a receiver knows that communication is complete (a process known as completion detection) when but only when m bits set to the predetermined value have been received (receipt of more than m bits is considered a violation of a precondition and is not catered to by the logic). An example of an m-of-n code is dual rail encoding (a 1-of-2 code), where each bit of data is encoded using first and second coded bits. The first coded bit is set to ‘1’ if the value to be encoded is ‘0’ while the second coded bit is set to ‘1’ is the value to be encoded is a ‘1.’ Dual rail systems are relatively straightforward to implement, although relatively inefficient.
The use of 1-of-4 codes for data communication has recently been proposed. A 1-of-4 code allows two bits to be transmitted using a single signal transition, that is two bits can be represented using exactly half the number of signals required by a dual rail encoding.
Efficiency of an m-of-n code can be defined by two metrics, rate R, and redundancy r which are defined by the following equations:
                    R        =                                            log              2                        ⁢                          m              s                                n                                    (        1        )                                r        =                  n          -                                    log              2                        ⁢                          m              s                                                          (        2        )            where ms is the number of discrete data symbols which can be represented by the code.
It is desirable to maximize rate, while minimizing redundancy. From equations (1) and (2) it can be deduced that a dual rail code has a rate of 0.5 and a redundancy of 1, while a 1-of-4 code has a rate of 0.5 and a redundancy of 2. However, the reduction of signal transitions required by a 1-of-4 code may render its use preferable in cases where power consumption is to be minimized.
In general terms, 1-of-n codes (which are a subset of m-of-n codes) are particularly easy to implement, given that completion detection can be carried out by using a straightforward OR function of all bits of the word. Thus 1-of-n codes are often used for delay insensitive communication. However, it should be noted that the efficiency of codes in which n is greater than four decreases considerably.
While using codes with a larger m value can improve rate and redundancy, (a 2-of-4 code allows six values to be represented and, from equations (1) and (2), has a rate of 0.65 and a redundancy of 1.412), the complexity of the required logic circuits is considered to be too expensive.
It is an object of the present invention to provide an improved coding method.